The disclosure relates to a vertical channel transistor in a semiconductor device and a method of fabricating the same, and more particularly, to a vertical channel transistor in a semiconductor device which can reduce resistance of a word line, and a method of fabricating the same.
As semiconductor devices become highly integrated, their cell area on a wafer is decreased. Since a transistor of a Giga-bit Dynamic Random Access Memory (DRAM) device requires a unit cell pitch of 4F2 (where F is the minimum feature size), a vertical channel transistor is provided in order to improve cell efficiency by increasing the integration degree of the DRAM device and securing an acceptable channel length of the transistor.
FIG. 1 is a perspective view of a semiconductor device having a vertical channel transistor of a type known to the inventor(s).
Referring to FIG. 1, the known vertical channel transistor includes a plurality of active pillars 190 vertically protruding from a semiconductor substrate 100. The active pillars 190 are formed by etching the semiconductor substrate 100 using a hard mask pattern (not shown) as an etch mask, and are arranged in a first direction A-A′ and a second direction B-B′ that crosses the first direction.
An impurity region (not shown) is formed by implanting impurities into regions between the active pillars 190 in the semiconductor substrate 100. An upper region and a lower region of the active pillar 190 are defined as a source region and a drain region, respectively. A channel region is vertically located in the active pillar 190 between the source region and the drain region. A bit line 110 is formed by dividing the impurity region through a device isolation trench 191, which extends in the second direction B-B′ of the semiconductor substrate 100. Also, a word line 193 is formed to electrically connect gate electrodes (not shown), which surround lower sidewalls of the active pillars 190, and extends in the first direction A-A′.
A storage electrode 195 is formed over the active pillar 190, and a contact plug 194 may be interposed between the active pillar 190 and the storage electrode 195.
FIGS. 2A to 7C illustrate a method of fabricating a vertical channel transistor in a semiconductor device as known to the inventor(s). Particularly, FIGS. 2A, 3A, 4A, 5A, 6A and 7A represent plan views of the semiconductor device being fabricated through multiple steps. FIGS. 2B, 3B, 4B, 5B, 6B and 7B represent cross-sectional views of FIGS. 2A, 3A, 4A, 5A, 6A and 7A taken along a cross-sectional line in the first direction A-A′, respectively. FIGS. 2C, 3C, 4C, 5C, 6C and 7C represent cross-sectional views of FIGS. 2A, 3A, 4A, 5A, 6A and 7A taken along a cross-sectional line in the second direction B-B′, respectively.
Referring to FIGS. 2A to 2C, an upper portion of an active pillar 190 is formed by etching a substrate 100 to a first predetermined depth using a hard mask nitride layer 101 as an etch mask. A pad oxide layer 102 may be interposed between the substrate 100 and the hard mask nitride layer 101. A spacer 103 is formed to protect sidewalls of the hard mask nitride layer 101, the pad oxide layer 102 and the upper portion of the active pillar 190. A lower portion of the active pillar 190 is formed by etching the substrate 100 to a second predetermined depth, which is greater than the first predetermined depth, using the hard mask nitride layer 101 and the spacer 103 as an etch barrier. The lower portion of the active pillar 190 is still connected with the upper portion of the active pillar 190 as a single body. An isotropic etching process is performed on the exposed substrate 100 in such a manner that the width of the active pillar 190 in the lower portion is narrower than the width of the active pillar 190 in the upper portion.
A gate insulation layer 104 is formed over the substrate 100 exposed by the hard mask nitride layer 101 and the spacer 103, and a gate electrode 105 surrounding the lower portion of the active pillar is formed. An impurity region for bit line formation is formed by implanting ion impurities into the substrate 100 between the active pillars 190.
An etch stop layer 106 is formed over the resultant structure including the gate electrode 105. A bottom of a gap region between the active pillars 190 is etched to a predetermined depth in the second direction to form a device isolation trench. Thus, the device isolation trench divides the impurity region to form a bit line 110. A first insulation layer 107 is formed over the resultant structure to fill the gap region between the active pillars 190.
A line-type mask pattern 112 is formed over the resultant structure to expose a line of the active pillars 190 arranged in the first direction. A spacing in the second direction between the adjacent mask patterns 112 is formed to be narrower than a width in the second direction of the active pillar 190.
Referring to FIGS. 3A to 3C, the first insulation layer 107 is etched by using the mask pattern 112 as an etch mask. The first insulation layer 107 is etched from the top surface thereof as shown in FIG. 2B to 2C, beyond the uppermost part of the gate electrode 105, down to a level lower by a predetermined height (FIG. 3B), and the first insulation layer 107 remains in the gap region between the active pillars 190 (FIG. 3C). In the etching process of the first insulation layer 107, the hard mask nitride layer 101 formed on the active pillar 190 may be damaged.
Referring to FIGS. 4A to 4C, the portion of the etch stop layer 106 that is exposed due to the etching process of the first insulation layer 107 is removed, and a word line trench is formed. The word line trench exposes the gate electrode 105 surrounding sidewalls of the lower region of the active pillar 190. As shown in FIG. 4A, only the portions of the etch stop layer 106 that is exposed by the mask pattern 112 is removed. Thus, not the whole gate electrode 105, but only a portion thereof, is exposed. In the process of removing the etch stop layer 106, the hard mask nitride layer 101 formed on the active pillar 190 may be further damaged.
As shown in FIGS. 5A to 5C, a conductive layer 108 is deposited over the resultant structure.
Referring to FIGS. 6A to 6C, an etch-back process is performed on the conductive layer 108 to a level of the uppermost part of the gate electrode 105, thereby forming word lines 108A. Each of the word lines 108A electrically connects the gate electrodes 105 of neighboring active pillars 190 and extends in the first direction. In the etch-back process of the conductive layer 108, the hard mask nitride layer 101 formed on the active pillar 190 may be damaged further.
Referring to FIGS. 7A to 7C, a second insulation layer 109 is deposited over the resultant structure including the word lines 108A to fill the gap region between the active pillars 190. Subsequently, the upper region of the active pillar 190 is exposed by removing the overlying portion of the second insulation layer 109 and the hard mask nitride layer 101. Then, a contact plug, e.g., 194 in FIG. 1, and a storage electrode, e.g., 195 in FIG. 1, are formed in the recited order over the exposed active pillar 190.
Resistance of the word line 108A as formed by the known method is disadvantageously large. Specifically, the conductive layer 108 is formed over the word line trench formed by removing portions of the etch stop layer 106, which are exposed by the selective etching of the first insulation layer 107. Thus, in a part 150 (FIG. 6A) where the etch stop layer 106 remains, the word line 108A cannot be connected to the gate electrode 105 surrounding the lower region of the active pillar 190. The contact area between the word line 108A and the gate electrode 105 is less than 360 degrees circumferentially of the gate electrode 105, and therefore, resistance of the word line 108A becomes disadvantageously large.
Also, at the formation of the word line trench (see FIGS. 3A to 3C), selectively removing of the etch stop layer 106 (see FIGS. 5A to 5C), and etch-back process of the conductive layer 108 (see FIGS. 6A to 6C), a large amount of the hard mask nitride layer 101 on the active pillar 190 is damaged. When the hard mask nitride layer 101 is damaged, the active pillar 190 below the hard mask nitride layer 101 is exposed and the active pillar may be damaged.
Meanwhile, when the hard mask nitride layer 101 is deposited thickly to prevent exposure of the active pillar 190 due to excessive damage to the hard mask nitride layer 101, the active pillar 190 may be collapsed due to the increased weight of the thick hard mask nitride layer 101. Also, there is a limitation to the increase of the thickness of the hard mask nitride layer 101 in consideration of the integration degree of the semiconductor device.